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74LVC373AD-Q100 Datasheet, PDF

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74LVC373AD-Q100 Part Attribute

  • Description The 74LVC373A-Q100 consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable input (pin LE) and an output enable input (pin OE) are common to all internal latches. When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latches are transparent, that is, a latch output changes each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. The 74LVC373A‑Q100 is functionally identical to the 74LVC573A‑Q100, but has a different pin arrangement. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
  • Part No. 74LVC373AD-Q100
  • Manufacturer 安世-Nexperia

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